1. Field of the Invention
The present invention relates to semiconductor memories and, more particularly, a non-volatile memory of the CAM type, i.e., capable of being addressed by means of its content.
2. Description of the Related Art
As is known, semiconductor memories, such as used in microprocessors, computers, and the like, consist of a large number of cells arranged in rows and columns to form a cell matrix. Each cell contains a binary information element (bit) and to each row of the matrix there corresponds a binary word whose length depends on the number of columns.
At present the most widely used memories are the static and dynamic RAMs (Random Access Memories) in which the word memorized in a row of the matrix can be accessed by simply furnishing its address. In the case of a CAM cell matrix, on the other hand, a binary word stored in a row can be looked for by inserting the word to be found in a comparison register associated with the matrix and comparing the content of the comparison register with the content of each row. The result of the search is made available by means of the observation of the voltage of a match line common to all the cells of a row. In particular, if the value of each bit of the word contained in the register coincides with that of the corresponding bit of the word of the row in question, the voltage of the match line will remain unchanged at a pre-charge value, while failure of even a single bit to coincide with its counterpart in the other binary word will cause the voltage of this line to assume ground value. In a cell matrix, obviously, this operation is carried out simultaneously for all the binary words of each row. In other words, a CAM memory is accessed by means of a comparison with its specific content rather than by means of a specific address.
There exist both volatile CAM cells and non-volatile CAM cells. The volatile CAM cells were initially developed from static RAM cells (SRAM) by simply adding transistors in such a manner as to provide an output connected to a match line. More recently, dynamic RAM cells (DRAM) have also been used as basic cells to obtain advantages in terms of area and cost.
CAM cells, irrespective of whether they are made with SRAMs or DRAMs, are relatively fast, but their binary content is lost as soon as the supply voltage is switched off. They therefore have to be rewritten at every new start-up by using a separate non-volatile memory unit, a hard disk for example. In CAMs of a non-volatile type, on the other hand, the data remain stored even when the voltage is cut off and, what is more, each cell calls for a smaller number of transistors and therefore a smaller silicon area than cells realized with SRAMs and DRAMs.
A known non-volatile CAM memory cell 210, as described for example in U.S. Pat. No. 6,317,439 B1 and shown in FIG. 1 of the drawings attached hereto, comprises two transistors 211, 212 of the floating-gate type that have their gate terminals connected to the same word line (WL) 220, their source terminals both connected to a match line (ML) 230 and their drain terminal each connected to one of the bit lines (BL,BL) 241, 242. In general, any non-volatile memory element could take the place of the two transistors. A multiplicity of cells equal to the cell 210 of FIG. 1, ordered in rows and columns, forms a CAM memory matrix, schematically represented in FIG. 2, where each row of cells comprises a pair of electric lines, respectively a word line 220 and a match line 230, and each column comprises two bit lines indicated by 241, 242.
As may be noted, all the word lines 220 are connected to an external row control block 360, the match lines 230 have one of their ends connected to this same block 360, while at the other end they terminate in sense amplifiers 380. Pilot circuits 371 and 372 are coupled, respectively, with the bit lines 241 and 242 to bias them during the search, writing, and cancelling operations. All the bit lines of the matrix lead to a block 370 that performs the function of register and control circuit for the search. The block 370 may contain a word for comparison purposes that is applied to its terminal indicated by DATA IN. The line control block 360 applies adequate voltages to the word lines and the match lines during the search, writing, and cancelling operations by selecting one row of the cell matrix on the basis of an input signal ADRIN. The sense amplifiers 380 detect a voltage variation on the respective match lines 230 when the input word, contained in block 370, does not coincide with the word memorized in the corresponding row of the matrix.
The threshold voltages of the transistors 211, 212 can be modified by acting on the terminals thereof to vary the electric charges of the respective floating-gates. The threshold voltage is determined by technological and design parameters and is “low” when electrons are not accumulated in the floating-gate transistors and “high” when they are being accumulated. The high threshold voltage is fixed at a value grater than the supply voltage Vcc of the memory circuits (for example Vcc=5V), while the low voltage, as a general rule, is not greater than 1 V. Conventionally, when the threshold voltage of the transistor 211 is set high, while that of transistor 212 is set low, the elementary information stored in the cell 210 is a logic 1. When the thresholds are set in the opposite manner, a logic 0 is memorized. It is also possible to memorize a third state X, known as the don't care state, by programming the thresholds of both elements to be high (>Vcc). The associative memories capable of memorizing these three states, rather than just the two basic logic states, are known as ternary memories. They are particularly advantageous in some applications.
Before undertaking the programming, the information content of the cell is cancelled by applying a sufficiently negative voltage to the word line 220 (for example, from −8V to −10V) and a positive voltage to the match line 230 (for example from 5V to 7V). The combination of these voltages on the gate and source terminals of the transistors 211, 212 causes a tunnel effect capable of removing electrons from the floating gate of the transistor that has the high threshold voltage and thus reducing it to the low threshold voltage. This operation exerts an effect (of lesser entity) also on a transistor already set to a low threshold voltage. One therefore needs appropriate algorithms to re-program the cells that have had their thresholds excessively lowered and thus obtain a well controlled final value. The value of the voltage on the bit lines 241, 242 does not exert any effect on the cancellation.
The operation of writing a CAM cell 210 is carried out by applying a high voltage to the word line 220 (for example, 8V) and setting the match line at ground voltage. When a logic 1 is to be memorized, the threshold of transistor 211 has to be stepped up, leaving the threshold of transistor 212 low, and one therefore applies an intermediate voltage (5V, for example) to the bit line 241, leaving the other bit line 242 unconnected. To memorize a logic 0, on the other hand, one operates on the bit lines in the opposite manner to raise the threshold of transistor 212. When the don't care state X has to be memorized, the intermediate voltage is applied to both the bit lines 241 and 242.
The search operation in the cell 210 is performed by applying the supply voltage VCC to the word line 220, pre-changing the match line 230 with the voltage VCC and applying appropriate voltages to the bit lines 241, 242. In particular, when the memorized data is a logic 1 (threshold of 211 high, threshold of 212 low) and the same bit is looked for in the cell, the bit line 241 is connected to ground, while the bit line 242 is connected to the supply voltage VCC. In that case, since neither of the transistors 211, 212 conducts, the voltage on the match line does not change, thus confirming that the stored bit matches the looked-for bit. When a logic 0 is being looked for, the bit lines have to be biased in the manner opposite to the previous case, so that this time it will be the transistor 212 that has the low threshold, conducts and therefore tends to reduce the voltage of the match line 230 to ground. When the memorized state is X, neither of the two transistors 211 and 212 can conduct and therefore looked-for bit and the memorized bit will always coincide.
The operations that have just been described are carried out simultaneously in all the cells of each row of the matrix. When the word contained in block 370 is found in a row of the matrix, the voltage of the match line corresponding to that row does not vary and the sense amplifier 380 connected to that match line provides a signal to a priority encoding block 385 that generates an output signal ADROUT that identifies the position in the matrix of the word that corresponds to the looked-for word. Vice versa, when the two words differ by even a single bit, the amplifier 380 detects the voltage variation on the match line and no output signal is generated.
In the described memory matrix, the low threshold of the transistors 211, 212 should be accurately controlled to assure that it will always be above a minimum predetermined value, 0.5 V for example. In this connection, let us now consider a matrix cell in which a bit is memorized (i.e., one of the transistors 211, 212 has a low threshold). If this cell forms part of a row in which there is no match when the previously described search operation is carried out, the voltage of the corresponding match line will always tend to assume the ground voltage. During the search it may happen that the gate and drain terminals of one of the two transistors 211, 212, the one with the low threshold, are at the voltage VCC and that the voltage difference between the gate terminal and the source terminal (connected to the match line) of the same transistor exceeds its threshold voltage when the potential of the match line approaches ground voltage. In that case the transistor under consideration will conduct a parasitic current that charges the match line and increases as the gate-source voltage becomes greater. If several cells in the same row conduct such parasitic currents, the voltage of the match line will not be sufficiently different from its initial pre-charge value (for example, VCC), so that, in a limited case, it may become difficult to detect a non-match during the search. The effect of the parasitic currents can be neglected for the purposes of signal generation on the match line only when the low threshold voltage of the transistors 211, 212 is greater than 0.5V. This sets some very restrictive constraints as far as the cancellation algorithm is concerned, which will have to become more and more accurate as the voltage applied to the word line diminishes. For example, a voltage of 1.8V on the word line would imply that all the low threshold voltages of all the cells would have to lie between 0.5V and 1V. There still remains the problem of dissipating the power due to the parasite currents. The worst case occurs when there is a match condition for half the cells in a row and a non-match condition for the other half. The match line voltage comes down to a value intermediate between Vcc and ground and a resistive path comes into being between the two potentials.
One should also consider the unfavorable, though not by any means unusual case in which none of the cells of a column of the matrix produce a match, while all the other cells in the matrix are in a match condition; in that case the current passing through one of the bit lines associated with that column has to discharge the capacitance associated with all the match lines of the matrix. In every cell forming part of the column under consideration, indeed, one of the transistors 211 or 212, when conducting, will connect one of the bit lines, which is at ground potential, to the match line of the row that contains the cell that is at the voltage VCC. The match lines to be discharged constitute a relatively high overall capacitative load (for example, 100 pF); in this particular case, therefore, the described matrix will need a relatively long time for carrying out the search operation.
When only one cell in a row of the described cell matrix is devoid of a match, the discharge of the match line associated with that row is slower than in the case where a match is lacking in several cells. With a view to speeding up the search operation and also to reduce the dissipation during the switching, the voltage excursion of the match line is reduced by making sure that the voltage of that line will not arrive at ground voltage (starting from the voltage VCC), but rather at a low value always greater than ground. This is obtained by using adequate voltage recovery circuits outside the memory matrix and connecting them to the match line during the search. However, the addition of the of the recovery circuits complicates the circuit structure of the known memory described above.